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Introduction to Sequential Circuits:

Understanding Flip-Flop:

The Basic R-S FLIP-FLOP

Consider the above schematic circuit of MC724 quad 2-input NOR gate of R-S Flip-Flop. When power is switched on and no inputs are applied(R=0 and S=0), due to imbalance of the circuit let say Q3 goes into conduction and Q1 and Q2 are in cut-off. Since Q3 is conducting, output at its collector will be zero i.e.Q=0 and Q2 is in cut-oof, it has maximum output voltage at its collector terminal 3 i.e. Q bar=1. The flip-flop is said to be in the  RESET position. This is one stable state as shown below.

When the inputs S=1 and R=0, Q1 goes into conduction, making Q bar=0. This makes the collector of Q3 and Q4 high giving Q=1. The flip-flop is now in another stable state i.e SET state and will remain in this state if no input is applied further as shown below.



Similarly, inputs S=0 and R=1 will change state to RESET the flip-flop i.e. Q=0. That means we write 0 into the flip-flop.

If S=1,R=0, we write 1 into memory as Q=1 as shown below. Thus set input makes Q high, a reset input makes Q low.

Symbol of R-S Flip-Flop is as follow.

So,from this the truth of R-S Flip-Flop as follow.

Watch the following video for animation of R-S Flip-Flop

Additional References:

(1) http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/16-flipflops/10-srff/srff.html

(2) http://www.falstad.com/circuit/e-nandff.html

(3) http://www.mekanizmalar.com/sr_flip_flops.html

(4) http://openbookproject.net/electricCircuits/Digital/DIGI_3.html

(5) http://www.play-hookey.com/digital/rs_nor_latch.html

(6) http://www.briarcliff.edu/departments/cis/CSCI280/Digital%20Logic/Flip-Flop%20SR%20Animation.gif

Assignment:

(1) Click on following image and go through the tutorial of Flip-Flop and upload the answer of quiz in it.

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